1. Field of the Invention
The present invention relates to column selecting circuits in semiconductor memory devices, and, more particularly, to a column selecting circuit in a semiconductor memory device in which a memory cell array is divided into a plurality of blocks, and corresponding bit lines in respective blocks are simultaneously selected.
2. Description of the Background Art
FIG. 9 is a block diagram illustrating a structure of a conventional semiconductor memory device (for example, a dynamic RAM). FIG. 9 illustrates only a memory cell array and a column selecting system for the sake of simplicity. A memory cell array MCA is provided with a plurality of word lines, a plurality of bit line pairs arranged crossing the word lines at right angles, and a plurality of memory cells arranged at respective crossings of the word lines and the bit line pairs. A sense amplifier group SAG includes a plurality of sense amplifiers provided for respective bit line pairs. Each sense amplifier amplifies data read from a memory cell to a bit line pair or data transmitted from the outside to a bit line pair. A column decoder CD decodes an externally applied column address and provides a signal for selecting one bit line pair out of a plurality of bit line pairs.
There is a tendency for the memory capacity of a semiconductor memory device to be further increased with the rapid advance in semiconductor technology in recent years. This causes the length of a bit line to be longer and the number of memory cells connected to one bit line to be increased. As a result, there has been a problem of capacitance of a bit line being increased and the speed of reading and writing being decreased.
A semiconductor memory device is proposed, in which a memory cell array is divided into a plurality of blocks, and selection of a bit line is individually carried out in each block to reduce capacitance of a bit line. For example, a semiconductor memory device illustrated in FIG. 10 includes a memory cell array divided into four blocks, i.e. memory cell arrays MCA1-MCA4. Each of memory cell arrays MCA1-MCA4 includes a sense amplifier group SAG1-SAG4 and a column decoder CD1-CD4. A column address is once supplied as an input to a predecoder PD and is predecoded. Predecoded signals provided from predecoder PD are applied to column decoders CD1-CD4, respectively. Each of column decoders CD1-CD4 further decodes the applied predecoded signal and selects one bit line pair in the corresponding memory cell array. Predecoder PD serves to select one memory cell array out of memory cell arrays MCA1-MCA4.
Although it is possible to reduce capacitance of a bit line in the semiconductor memory device illustrated in FIG. 10, it is necessary to provide a column decoder for each memory cell array, and there is another problem that the area of circuits is increased.
A semiconductor memory device is proposed, in which the column decoders which were provided individually in respective memory cell arrays are implemented to be a common one to reduce the area of the circuits. FIG. 11 is a block diagram illustrating an example of such a semiconductor memory device. Each memory cell array is provided with a plurality of common column selecting lines CSL. A column decoder CD selectively drives one of the plurality of column selecting lines CSL on the basis of an externally applied column address. This causes corresponding bit line pairs in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Accordingly, data are simultaneously provided from sense amplifier groups SAG1-SAG4, and one of the data is selected by a selector SEL and provided as an output.
FIG. 12 is a block diagram illustrating a further detailed structure of the conventional semiconductor memory device illustrated in FIG. 11. A column address buffer CAB includes a plurality of one-bit buffers BB0-BB11 and converts externally applied column addresses A0-A11 into appropriate signals CA0, /CA0-CA11, /CA11 to be used in the semiconductor memory device, as illustrated in FIG. 13. Signals CA2, /CA2-CA9, /CA9, and CA11, /CA11 are supplied to a predecoder PD and predecoded. As illustrated in FIG. 14, predecoder PD includes a plurality of subdecoders DC01-DC04 and provides predecoded signals Y4-Y23. Predecoded signals Y4-Y23 are supplied to a column decoder CD. As illustrated in FIG. 15, column decoder CD includes a plurality of column drivers DRV. One of predecoded signals Y4-Y7, one of predecoded signals Y8-Y11, one of predecoded signals Y12-Y15, and one of predecoded signals Y16-Y23 are applied to each column driver DRV. Each column driver DRV is activated and drives a corresponding column selecting line CSL when all the predecoded signals applied from predecoder PD are at an active level (for example, at a high or "H" level).
As illustrated in FIG. 16, each of memory cell arrays MCA1-MCA4 is provided with a plurality of word lines WL, a plurality of bit line pairs BL, /BL arranged to cross word lines WL at right angles, and memory cells MC arranged at respective crossings of the word lines and the bit line pairs. Each of sense amplifier groups SAG1-SAG4 includes sense amplifiers SA provided for respective bit line pairs in a corresponding memory cell array. Each sense amplifier SA is connected through a corresponding transfer gate TG to a corresponding input/output line pair IO, /IO. Each input/output line pair IO, /IO is connected to a selector SEL. Column selecting lines CSL are provided, for example, at a ratio of one column selecting line to four bit line pairs. Each column selecting line CSL is connected to gates of transistors constituting transfer gates TG of corresponding bit line pairs.
If one word line WL is selected by a row decoder not shown, stored data are read from the memory cells connected to the selected word line and transmitted to corresponding bit line pairs, respectively.
Subsequently, if one of column selecting lines CSL is driven by column decoder CD, four transfer gates TG are simultaneously turned on in respective memory cell arrays MCA1-MCA4. Therefore, four bit line pairs corresponding to the selected column selecting line CSL are selected in each of memory cell arrays MCA1-MCA4. The data read to each of the selected bit line pairs is transmitted through a corresponding sense amplifier SA, a transfer gate TG, and an input/output line pair IO, /IO to selector SEL.
Selector SEL selects a read data transmitted from one of the bit line pairs in one of the memory cell arrays on the basis of signals CA0, /CA0, CA1, /CA1, CA10, /CA10 applied from column address buffer CAB and provides it as an output.
As described above, according to a conventional semiconductor memory device illustrated in FIG. 12, corresponding bit line pairs in respective memory cell arrays MCA1-MCA4 are simultaneously selected by one common column decoder CD, so that the area of the circuits can be reduced in comparison with the semiconductor memory device including a column decoders for each memory cell array illustrated in FIG. 10.
According to the semiconductor memory device illustrated in FIG. 12, however, there is a problem of the wiring structure for predecoded signals Y4-Y23 between predecoder PD and column decoder CD. Specifically, as illustrated in FIG. 15 or FIG. 8, the conventional semiconductor memory device illustrated in FIG. 12 has all the signal lines for transmitting respective predecoded signals Y4-Y23 to column decoder CD arranged to cover the whole length of column decoder CD. Therefore, the length of wiring for each predecoded signal is made unnecessarily long, and capacitance of wiring is increased. As a result, delay in transmission of the predecoded signal is increased, and power consumption is also increased. In addition, the area of a layout for wiring for the predecoded signal is increased.